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Chapter 1: XM104
Board Technical Description
The XM104 provides a number of connectors which break out the FPGA multi-gigabit
transceiver (MGT) interface signals to and from the board interface. Figure 1-2 shows a
block diagram of the XM104. Each MGT data port interface consists of two differential
pairs of MGT signals, one pair for the transmitter and one pair for the receiver. MGT Data
Ports 0 and 1 are each wired to four SMA connectors. MGT Data Ports 2 and 3 are each
wired to host Serial ATA connectors J11 and J12 respectively. MGT Data Ports 4 through 7
are wired to a 10GE Base-CX4 connector supporting a XAUI application interface. MGT
transmitter Data Ports 8 and 9 are electrically looped back to the board receiver ports 8 and
9 respectively. The ML605 does not support Data Port 8 and 9 interfaces.
Silicon Laboratories Si570 serial IIC bus reprogrammable LVDS clock source and a Si5368
any-rate precision clock multiplier and jitter attenuator integrated circuits provide a
variety of programmable differential clock sources to the board’s FGPA. The Si5368
integrated circuit receives three differential LVDS clock inputs from the board and outputs
five LVDS differential clock outputs to the FPGA.
A 2 Kb serial IIC EEPROM is also connected to the IIC interface of the board providing
non-volatile storage. The serial IIC interface also connects to the Si570 and Si5368
integrated circuits enabling the board’s FPGA to program the clock circuitry on the XM104.
X-Ref Target - Figure 1-2
J1 FMC HPC Interf a ce
S i5 3 68
MGT D a t a Port 0
S MA (4x)
J 3 , J4, J5, J6
MGT D a t a Port 1
S MA (4x)
DP0
DP1
GBTCLK0_M2C
CLK0_M2C
CLK1_M2C
CLK2_M2C
CLK 3 _M2C
CKOUT1
F S _OUT
CKOUT2
CKOUT 3
CKOUT4
J7, J8, J9, J10
Level
S hifter
Any-r a te Clock
MGT D a t a Port 2
S eri a l ATA J11
MGT D a t a Port 3
S eri a l ATA J12
DP2
DP 3
LA00_CC
LA01_CC
LA17_CC
CKIN1
CKIN 3
CKIN4
CKIN2
S i570
MGT D a t a Port s 4-7
10GE B as e-CX4 J2
MGT D a t a Port s 8-9
Electric a l Loop ba ck
DP4-DP7
DP8-DP9
IIC
S witch
Clock
156.25 MHz
Clock
Driver
2 K b
IIC
EEPROM
GBTCLK1_M2C
UG5 3 6_02_120 3 09
Figure 1-2:
XM104 Block Diagram
10
www.xilinx.com
FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
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